Design for hierarchical testability of RTL circuits obtained by behavioral synthesis

Computer Science

• Test Generation 100%
• Register-Transfer Level 100%
• Density Functional Theory 40%
• Data Controller 40%
• High Level Synthesis 20%
• Fault Coverage 20%
• Generation Time 20%
• Design Hierarchy 20%

Engineering

• Testability 100%
• Data Path 100%
• Test Level 40%
• Area Overhead 20%
• High Level Synthesis 20%

Keyphrases

• Behavioral Design 33%
• Controller Circuit 33%