Design for hierarchical testability of RTL circuits obtained by behavioral synthesis

Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha

Research output: Contribution to journalArticle

30 Scopus citations

Abstract

In recent years, there has been growing interest in behavioral (high-level) synthesis for testability. This is due to the fact that testability features, such as scan or the built-in self-test, may incur large overheads if introduced during logic synthesis in the later phase of the design cycle. Related previous work attempted to generate system-level test sets using hierarchical testability during behavioral synthesis. There, the test generation scheme is independent of bit width and is, therefore, capable of handling complex controller/data path circuits with large data path bit widths (e.g., 32), which has posed a serious challenge to logic-level sequential test generators. However, this previous work is not applicable when another high-level synthesis system is used. In this paper, we present techniques that add minimal test hardware to a given register-transfer level (RTL) circuit obtained by behavioral synthesis in order to ensure that the embedded elements in the circuit are hierarchically testable. An important byproduct of our design for testability (DFT) procedure is a system-level test set that delivers precomputed test sets to each element in the RTL circuit. This eliminates the need to apply gate-level sequential test generation to the combined controller/data path. We performed extensive experiments with several complex controller/data path circuits synthesized by three different high-level synthesis systems which do not target testability. The key advantages of our method, illustrated by these experiments, include: 1) the area, delay, and power overheads incurred for testability are very low (the average area, delay, and power overheads for a large number of benchmarks are 3.5, 0.5, and 3.4%, respectively), 2) both the DFT hardware addition and test generation algorithms are independent of the data path bit width (we generate test sets which have over 99% fault coverage in all the cases), 3) in test generation times, our method is 2-to-4 orders of magnitude faster than efficient gate-level sequential test generators and 1-to-3 orders of magnitude faster than efficient gate-level combinational test generators which assume full scan, and 4) unlike many other DFT methods, a large part of our system-level test sets can be applied at speed. In addition, if C-testable modules are used in the data path, then the test application times are also comparable with that of gate-level sequential test generation. Even when such modules are not used, the test application times are 1-to-2 orders of magnitude smaller than what full scan would require.

Original languageEnglish (US)
Pages (from-to)1001-1014
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume16
Issue number9
DOIs
StatePublished - Dec 1 1997

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Keywords

  • Controller/data path testability
  • Design for testability
  • Hierarchical testing
  • Symbolic test generation

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