Design and implementation of virtual memory-mapped communication on Myrinet

Cezary Dubnicki, Angelos Bilas, Kai Li, James Philbin

Research output: Contribution to journalConference article

23 Scopus citations

Abstract

This paper describes the design and implementation of the virtual memory-mapped communication model (VMMC) on a Myrinet network of PCI-based PCs. VMMC has been designed and implemented for the SHRIMP multicomputer where it delivers user-to-user latency and bandwidth close to the limits imposed by the underlying hardware. The goal of this work is to provide an implementation of VMMC on a commercially available hardware platform; to determine whether the benefits of VMMC can be realized on the new hardware; and to investigate network interface design tradeoffs by comparing SHRIMP with Myrinet and its respective VMMC implementation. Our Myrinet implementation of VMMC achieves 9.8 microseconds one-way latency and provides 108.4 MBytes per second user-to-user bandwidth. Compared to SHRIMP, the Myrinet implementation of VMMC incurs relatively higher overhead and demands more network interface resources (LANai processor, on-board SRAM) but requires less operating system support.

Original languageEnglish (US)
Pages (from-to)388-396
Number of pages9
JournalProceedings of the International Parallel Processing Symposium, IPPS
StatePublished - Jan 1 1997
EventProceedings of the 1997 11th International Parallel Processing Symposium, IPPS 97 - Geneva, Switz
Duration: Apr 1 1997Apr 5 1997

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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