Design and implementation of NX message passing using Shrimp virtual memory mapped communication

R. Alpert, C. Dubnicki, Edward William Felten, Kai Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

This paper describes the design, implementation and performance of the NX message-passing interface on the Shrimp multicomputer. Unlike traditional methods, our implementation, exploiting Shrimp's virtual memory-mapped communication facility, performs buffer management at user level without using a special message-passing processor, and requires no CPU intervention upon message arrival in the common cases. For a four-byte message, our implementation, achieves a user-To-user latency of 12 microseconds, about factor of four smaller than that on the Intel Paragon. For large messages, our implementation quickly approaches the bandwidth limit imposed by the Shrimp hardware.

Original languageEnglish (US)
Title of host publicationArchitecture
EditorsA. Reeves
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages111-119
Number of pages9
ISBN (Electronic)081867623X
DOIs
StatePublished - Jan 1 1996
Event25th International Conference on Parallel Processing, ICPP 1996 - Ithaca, United States
Duration: Aug 12 1996Aug 16 1996

Publication series

NameProceedings of the International Conference on Parallel Processing
Volume1
ISSN (Print)0190-3918

Other

Other25th International Conference on Parallel Processing, ICPP 1996
CountryUnited States
CityIthaca
Period8/12/968/16/96

All Science Journal Classification (ASJC) codes

  • Software
  • Mathematics(all)
  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Design and implementation of NX message passing using Shrimp virtual memory mapped communication'. Together they form a unique fingerprint.

  • Cite this

    Alpert, R., Dubnicki, C., Felten, E. W., & Li, K. (1996). Design and implementation of NX message passing using Shrimp virtual memory mapped communication. In A. Reeves (Ed.), Architecture (pp. 111-119). [537151] (Proceedings of the International Conference on Parallel Processing; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.1996.537151