Design and analysis of fault-detecting and fault-locating schedules for computation DAGs

Shalini Yajnik, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper investigates issues concerning the construction of fault-detecting and fault-locating schedules for multiprocessor systems. We develop conditions for a schedule to be fault-detecting or fault-locating and further use these conditions to propose schemes for construction of the schedules. Lowerbounds on the length of the schedules are calculated and for the special case of binary computation trees, it is shown that our schedules meet the lowerbounds in most cases. A method for actual fault diagnosis from the results of the fault-locating schedules for binary computation trees is also proposed.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherPubl by IEEE
Pages348-351
Number of pages4
ISBN (Print)0818626720
StatePublished - Dec 1 1992
EventProceedings of the 6th International Parallel Processing Symposium - Beverly Hills, CA, USA
Duration: Mar 23 1992Mar 26 1992

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

Other

OtherProceedings of the 6th International Parallel Processing Symposium
CityBeverly Hills, CA, USA
Period3/23/923/26/92

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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  • Cite this

    Yajnik, S., & Jha, N. K. (1992). Design and analysis of fault-detecting and fault-locating schedules for computation DAGs. In Proceedings of the International Conference on Parallel Processing (pp. 348-351). (Proceedings of the International Conference on Parallel Processing). Publ by IEEE.