Delay computation in combinational logic circuits: Theory and algorithms

Srinivas Devadas, Kurt Keutzer, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

28 Scopus citations

Abstract

The authors provide necessary and sufficient conditions for a path to be true in the floating mode of operation. Static cosensitization is introduced as a necessary condition, which allows one to avoid the problem of identifying false paths as responsible for delay. The results are extended to determine the truth or falsity of entire sets of paths simultaneously by expressing them in terms of the testability of a multifault in an ENF (equivalent normal form) expression. This result is applied directly to an unmodified multilevel circuit. Because the circuits that are most troublesome for false-path-eliminating static timing analyzers are those with millions of paths, and in particular millions of longest paths, the ability to handle entire sets of paths simultaneously results in a very efficient delay computation procedure. This is demonstrated by the results from a preliminary implementation of the algorithm.

Original languageEnglish (US)
Title of host publication1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
PublisherPubl by IEEE
Pages176-179
Number of pages4
ISBN (Print)0818621575
StatePublished - Dec 1 1992
Externally publishedYes
Event1991 IEEE International Conference on Computer-Aided Design - ICCAD-91 - Santa Clara, CA, USA
Duration: Nov 11 1991Nov 14 1991

Other

Other1991 IEEE International Conference on Computer-Aided Design - ICCAD-91
CitySanta Clara, CA, USA
Period11/11/9111/14/91

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Devadas, S., Keutzer, K., & Malik, S. (1992). Delay computation in combinational logic circuits: Theory and algorithms. In 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers (pp. 176-179). Publ by IEEE.