### Abstract

In this paper we propose a data structure for abstracting the delay information of a combinatorial circuit. The particular abstraction that we are interested in is one that preserves the delays between all pairs of inputs and outputs in the circuit. Such abstractions are useful when considering the delay of cascaded circuits in high-level synthesis and other such applications in synthesis. The proposed graphical data structure is called the concise delay network, and is of size proportional to (m + n) in best case, where m and n refer to the number of inputs and outputs of the circuit. In comparison, a delay matrix that stores the maximum delay between each input-output pair has size proportional to m x n. For circuits with hundreds of inputs and outputs, this storage and the associated computations become quite expensive, especially when they need to be done repeatedly during synthesis. We present heuristic algorithms for deriving these concise delay networks. Experimental results shows that, in practice, we can obtain concise delay network with the number of edges being a small multiple of (m+ra).

Original language | English (US) |
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Pages (from-to) | 1205-1212 |

Number of pages | 8 |

Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |

Volume | 16 |

Issue number | 10 |

DOIs | |

State | Published - Dec 1 1997 |

Externally published | Yes |

### All Science Journal Classification (ASJC) codes

- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering

### Keywords

- Combinational logic circuits
- data structures
- delay estimation
- directed graphs

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## Cite this

*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*,

*16*(10), 1205-1212. https://doi.org/10.1109/43.662683