Delay abstraction in combinational logic circuits

Noriya Kobayashi, Sharad Malik

Research output: Contribution to conferencePaper

Abstract

In this paper we propose a data structure for abstracting the delay information of a combinatorial circuit. The particular abstraction that we are interested in is one that preserves the delays between all pairs of inputs and outputs in the circuit. The proposed graphical data structure is of size proportional to (m + n) in best case, where m and n refer to the number of inputs and outputs of the circuit. In comparison, a delay matrix that stores the maximum delay between each input/output pair has size proportional to m × n. We present heuristic algorithms for deriving these concise delay networks. Experimental results shows that, in practice, we can obtain concise delay network with the number of edges being a small multiple of (m + n).

Original languageEnglish (US)
Pages453-458
Number of pages6
StatePublished - Dec 1 1995
Externally publishedYes
EventProceedings of the 1995 Asia and South Pacific Design Automation Conference, ASP-DAC'95 - Chiba, Jpn
Duration: Aug 29 1995Sep 1 1995

Other

OtherProceedings of the 1995 Asia and South Pacific Design Automation Conference, ASP-DAC'95
CityChiba, Jpn
Period8/29/959/1/95

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Kobayashi, N., & Malik, S. (1995). Delay abstraction in combinational logic circuits. 453-458. Paper presented at Proceedings of the 1995 Asia and South Pacific Design Automation Conference, ASP-DAC'95, Chiba, Jpn, .