Datapath merging and interconnection sharing for reconfigurable architectures

Nahri Moreano, Guido Araujo, Zhining Huang, Sharad Malik

Research output: Contribution to journalConference articlepeer-review

27 Scopus citations


Recent work in reconfigurable computing research has shown that a substantial performance speedup can be achieved through architectures that map the most relevant application inner-loops to a reconfigurable datapath. Any solution to this problem must be able to synthesize a datapath for each loop and to merge them together into a single reconfigurable datapath. The main contribution of this paper is a novel graph-based technique for the datapath merge problem. This approach is based on the solution of a maximum clique problem that merges datapaths one at a time. A set of experiments, using the MediaBench benchmark, shows that the proposed technique produces 24% fewer datapath interconnections than a previous solution to this problem.

Original languageEnglish (US)
Pages (from-to)38-43
Number of pages6
JournalProceedings of the International Symposium on System Synthesis
StatePublished - 2002
Event15th International Symposium on System Synthesis - Kyoto, Japan
Duration: Oct 2 2002Oct 4 2002

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


  • High level and architectural synthesis
  • Reconfigurable computing


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