Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications

Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core utilization. While prior work with prefetching, decoupling, or pipelining can mitigate memory latency and improve core utilization, memory bottlenecks persist due to limited off-chip bandwidth. Approaches doing processing in-memory (PIM) with Hybrid Memory Cube (HMC) overcome bandwidth limitations but fail to achieve high core utilization due to poor task scheduling and synchronization overheads. Moreover, the high memory-per-core ratio available with HMC limits strong scaling.We introduce Dalorex, a hardware-software co-design that achieves high parallelism and energy efficiency, demonstrating strong scaling with >16,000 cores when processing graph and sparse linear algebra workloads. Over the prior work in PIM, both using 256 cores, Dalorex improves performance and energy consumption by two orders of magnitude through (1) a tile-based distributed-memory architecture where each processing tile holds an equal amount of data, and all memory operations are local; (2) a task-based parallel programming model where tasks are executed by the processing unit that is co-located with the target data; (3) a network design optimized for irregular traffic, where all communication is one-way, and messages do not contain routing metadata; (4) novel traffic-aware task scheduling hardware that maintains high core utilization; and (5) a data-placement strategy that improves work balance.This work proposes architectural and software innovations to provide the greatest scalability to date for running graph algorithms while still being programmable for other domains.

Original languageEnglish (US)
Title of host publication2023 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023 - Proceedings
PublisherIEEE Computer Society
Pages718-730
Number of pages13
ISBN (Electronic)9781665476522
DOIs
StatePublished - 2023
Event29th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023 - Montreal, Canada
Duration: Feb 25 2023Mar 1 2023

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume2023-February
ISSN (Print)1530-0897

Conference

Conference29th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023
Country/TerritoryCanada
CityMontreal
Period2/25/233/1/23

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • Distributed
  • NoC
  • architecture
  • bandwidth
  • data-local
  • graph
  • near-memory
  • network
  • parallel
  • scalable
  • sparse

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