Coordinated, distributed, formal energy management of chip multiprocessors

Philo Juang, Qiang Wu, Li Shiuan Peh, Margaret Rose Martonosi, Douglas W. Clark

Research output: Contribution to journalConference articlepeer-review

56 Scopus citations


Designers are moving toward chip-multiprocessors (CMPs) to lever-age application parallelism for higher performance while keeping design complexity under control. However, to date, no power management techniques have been proposed for coordinated power control of multiple processor cores. In this paper, we illustrate how the use of local, per-tile dynamic voltage and frequency scaling (DVFS) techniques can result in tiles counteracting each others' power management policies, significantly hurting chip power-performance. We then propose a coordinated DVFS scheme for CMPs, which eliminates the oscillations and ensures efficient and resilient DVFS control. Specifically, our proposed technique incorporates thread information collected at run-time across the chip. In addition, by extending a control-theoretic local DVFS control technique toward DVFS for chip-multiprocessors, our technique prescribes DVFS settings formally at each tile, thus ensuring stable, distributed, coordinated DVFS control of a CMP. Experimental results show that our technique achieves a 15.5% improvement in energy-delay product over a CMP with no DVFS control, and a 7% improvement in energy-delay product against the latest state-of-the-art local DVFS scheme.

Original languageEnglish (US)
Pages (from-to)127-130
Number of pages4
JournalProceedings of the International Symposium on Low Power Electronics and Design
StatePublished - 2005
Event2005 International Symposium on Low Power Electronics and Design - San Diego, CA, United States
Duration: Aug 8 2005Aug 10 2005

All Science Journal Classification (ASJC) codes

  • General Engineering


  • Dynamic Voltage Scaling
  • Power


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