Control techniques to eliminate voltage emergencies in high performance processors

R. Joseph, D. Brooks, Margaret Rose Martonosi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

102 Scopus citations

Abstract

Increasing focus on power dissipation issues in current microprocessors has led to a host of proposals for clock gating and other power-saving techniques. While generally effective at reducing average power, many of these techniques have the undesired side-effect of increasing both the variability of power dissipation and the variability of current drawn by the processor This increase in current variability, often referred to as the dI/dt problem, can cause supply voltage fluctuations. Such voltage fluctuations lead to unreliable circuits if not addressed, and increasingly expensive chip packaging techniques are needed to mitigate them. This paper proposes and evaluates a methodology for augmenting packaging techniques for dI/dt with microarchitectural control mechanisms. We discuss the resonant frequencies most relevant to current microprocessor packages, produce and evaluate a «dI/dt stressmark» that exercises the system at its resonant frequency, and characterize the behavior of more mainstream applications. Based on these results plus evaluations of the impact of controller error and delay, our microarchitectural control proposals offer bounds on supply voltage fluctuations, with nearly negligible impact on performance and energy. With the ITRS roadmap predicting aggressive drops in supply voltage and power supply impedances in coming chip generations, novel voltage control techniques will be required to stay on track. Our microarchitectural dI/dt controllers represent a step in this direction.

Original languageEnglish (US)
Title of host publicationProceedings - 9th International Symposium on High-Performance Computer Architecture, HPCA 2003
PublisherIEEE Computer Society
Pages79-90
Number of pages12
ISBN (Electronic)0769518710
DOIs
StatePublished - Jan 1 2003
Event9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003 - Anaheim, United States
Duration: Feb 8 2003Feb 12 2003

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume12
ISSN (Print)1530-0897

Other

Other9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003
CountryUnited States
CityAnaheim
Period2/8/032/12/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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    Joseph, R., Brooks, D., & Martonosi, M. R. (2003). Control techniques to eliminate voltage emergencies in high performance processors. In Proceedings - 9th International Symposium on High-Performance Computer Architecture, HPCA 2003 (pp. 79-90). [1183526] (Proceedings - International Symposium on High-Performance Computer Architecture; Vol. 12). IEEE Computer Society. https://doi.org/10.1109/HPCA.2003.1183526