TY - JOUR
T1 - Configuration and extension of embedded processors to optimize IPSec protocol execution
AU - Potlapally, Nachiketh R.
AU - Ravi, Srivaths
AU - Raghunathan, Anand
AU - Lee, Ruby B.
AU - Jha, Niraj K.
N1 - Funding Information:
Manuscript received October 31, 2005; revised May 27, 2006. This work was supported by the National Science Foundation under Grant CCR-0326372. N. R. Potlapally, R. B. Lee, and N. K. Jha are with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA (e-mail: [email protected]; [email protected]; [email protected]). S. Ravi and A. Raghunathan are with NEC Laboratories America, Princeton, NJ 08540 USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TVLSI.2007.896912
PY - 2007/5
Y1 - 2007/5
N2 - Security protocols, such as IPSec and SSL, are being increasingly deployed in the context of networked embedded systems. The resource-constrained nature of embedded systems and, in particular, the modest capabilities of embedded processors make it challenging to achieve satisfactory performance while executing security protocols. A promising approach for improving performance in embedded systems is to use application-specific instruction set processors that are designed based on configurable and extensible processors. In this paper, we perform a comprehensive performance analysis of the IPSec protocol on a state-of-the-art configurable and extensible embedded processor (Xtensa from Tensilica Inc.). We present performance profiles of a lightweight embedded IPSec implementation running on the Xtensa processor, and examine in detail the various factors that contribute to the processing latencies, including cryptographic and protocol processing. In order to improve the efficiency of IPSec processing on embedded devices, we then study the impact of customizing an embedded processor by synergistically 1) configuring architectural parameters, such as instruction and data cache sizes, processor-memory interface width, write buffers, etc., and 2) extending the base instruction set of the processor using custom instructions for both cryptographic and protocol processing. Our experimental results demonstrate that upto 3.2 × speedup in IPSec processing is possible over a popular embedded IPSec software implementation.
AB - Security protocols, such as IPSec and SSL, are being increasingly deployed in the context of networked embedded systems. The resource-constrained nature of embedded systems and, in particular, the modest capabilities of embedded processors make it challenging to achieve satisfactory performance while executing security protocols. A promising approach for improving performance in embedded systems is to use application-specific instruction set processors that are designed based on configurable and extensible processors. In this paper, we perform a comprehensive performance analysis of the IPSec protocol on a state-of-the-art configurable and extensible embedded processor (Xtensa from Tensilica Inc.). We present performance profiles of a lightweight embedded IPSec implementation running on the Xtensa processor, and examine in detail the various factors that contribute to the processing latencies, including cryptographic and protocol processing. In order to improve the efficiency of IPSec processing on embedded devices, we then study the impact of customizing an embedded processor by synergistically 1) configuring architectural parameters, such as instruction and data cache sizes, processor-memory interface width, write buffers, etc., and 2) extending the base instruction set of the processor using custom instructions for both cryptographic and protocol processing. Our experimental results demonstrate that upto 3.2 × speedup in IPSec processing is possible over a popular embedded IPSec software implementation.
KW - Configurability
KW - Embedded processors
KW - Embedded security
KW - Embedded systems
KW - Extensibility
KW - IPsec
KW - Performance
KW - Security protocols
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U2 - 10.1109/TVLSI.2007.896912
DO - 10.1109/TVLSI.2007.896912
M3 - Article
AN - SCOPUS:34249820822
SN - 1063-8210
VL - 15
SP - 605
EP - 609
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 5
ER -