We compare the performance of three major programming models - a load-store cache-coherent shared address space (CC-SAS), message passing (MP) and the segmented SHMEM model - on a modern, 64-processor hardware cache-coherent machine, one of the two major types of platforms upon which high-performance computing is converging. We focus on applications that are either regular and predictable or at least do not require fine-grained dynamic replication of irregularly accessed data. Within this class, we use programs with a range of important communication patterns. We examine whether the basic parallel algorithm and communication structuring approaches needed for best performance are similar or different among the models, whether some models have substantial performance advantages over others as problem size and number of processors change, what the sources of these performance differences are, where the programs spend their time, and whether substantial improvements can be obtained by modifying either the application programming interfaces or the implementations of the programming models on this type of platform.
|Original language||English (US)|
|Number of pages||10|
|Journal||Proceedings of the International Conference on Supercomputing|
|State||Published - Jan 1 1999|
All Science Journal Classification (ASJC) codes
- Computer Science(all)