Communication reliability improvement for WSI array processors

J. S.N. Jean, S. Y. Kung

Research output: Contribution to journalConference articlepeer-review


A reconfiguration algorithm is proposed for two arrays, a one-and-half-track array and a two-and-half-track array. The algorithm considers a whole fault pattern all together and therefore makes no early blind decision. The reconfiguration algorithm can systematically enumerate all the placement possibilities and can handle the defects of switches/connections/wires by incorporating the restrictions into the contradiction graph. It is shown that much better array yield can be obtained for the two-and-half-track array. The one-and-half-track array, however, is still useful when run-time fault tolerance is considered.

Original languageEnglish (US)
Pages (from-to)796-800
Number of pages5
JournalConference Record - International Conference on Communications
StatePublished - 1990
Externally publishedYes
EventIEEE International Conference on Communications - ICC '90 Part 3 (of 4) - Atlanta, GA, USA
Duration: Apr 16 1990Apr 19 1990

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering


Dive into the research topics of 'Communication reliability improvement for WSI array processors'. Together they form a unique fingerprint.

Cite this