Abstract
A design tool called PLASTIC is presented which combines the space-saving advantages of multilevel decomposition are combined with logic minimization, topological partitioning, and a compact PLA layout style. It avoids the need for the logic designer to hand-partition a large and slow monolithic PLA, and automatically generates area-efficient multilevel PLAs. Initial results for PLASTIC show area savings of up to 40%.
| Original language | English (US) |
|---|---|
| Title of host publication | Unknown Host Publication Title |
| Publisher | IEEE |
| Pages | 112-115 |
| Number of pages | 4 |
| ISBN (Print) | 0818608145 |
| State | Published - 1987 |
| Externally published | Yes |
All Science Journal Classification (ASJC) codes
- General Engineering