Hardware-software co-synthesis (HSCS) of an embedded system is the process of partitioning, mapping and scheduling its specification into hardware and software modules to meet performance, cost, reliability and availability goals. The HSCS problem for fault-tolerant real-time heterogeneous distributed embedded systems is addressed. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. An algorithm, called COFTA (Co-synthesis Of Fault Tolerant Architectures) allows multiple types of assertions to be specified for each tasks. Application to a large number of real-life telecom transport system examples show the algorithm's efficacy.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics