Abstract
This paper examines the problem of code-generation for Digital Signal Processors (DSPs). We make two major contributions. First, for an important class of DSP architectures, we propose an optimal O(n) algorithm for the tasks of register allocation and instruction scheduling for expression trees. Optimality is guaranteed by sufficient conditions derived from a structural representation of the processor Instruction Set Architecture (ISA). Second, we develop heuristics for the case when basic blocks are Directed Acyclic Graphs (DAGs).
| Original language | English (US) |
|---|---|
| Pages (from-to) | 136-161 |
| Number of pages | 26 |
| Journal | ACM Transactions on Design Automation of Electronic Systems |
| Volume | 3 |
| Issue number | 2 |
| DOIs | |
| State | Published - 1998 |
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
Keywords
- Algorithms
- Code generation
- Register allocation
- Scheduling