Code generation for fixed-point DSPs

Guido Araujo, Sharad Malik

Research output: Contribution to journalArticle

14 Scopus citations

Abstract

This paper examines the problem of code-generation for Digital Signal Processors (DSPs). We make two major contributions. First, for an important class of DSP architectures, we propose an optimal O(n) algorithm for the tasks of register allocation and instruction scheduling for expression trees. Optimality is guaranteed by sufficient conditions derived from a structural representation of the processor Instruction Set Architecture (ISA). Second, we develop heuristics for the case when basic blocks are Directed Acyclic Graphs (DAGs).

Original languageEnglish (US)
Pages (from-to)136-161
Number of pages26
JournalACM Transactions on Design Automation of Electronic Systems
Volume3
Issue number2
DOIs
StatePublished - Jan 1 1998

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Keywords

  • Algorithms
  • Code generation
  • Register allocation
  • Scheduling

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