This paper introduces a new design methodology for incorporating process-sensitive optical nanostructures in standard CMOS processes to create robust optical physically unclonable functions (PUFs) realized through an electrical-photonic co-design approach. The passive lithographic variations of lower level metal interconnects are exploited to realize resonant photonic crystals on an array of photodetectors to include variations that are robust to noise processes. The chip is realized in a standard 65-nm CMOS process with no additional post-processing. The addition of the structures increases the coefficient of variation by a factor of 3.5 × compared to only active device variations. This creates extremely robust PUF responses with a native inter-chip Hamming distance (HD) of 49.81% and intra-chip HD of 0.251% with an inter-HD/ intra-HD ratio of 198 × illustrating the reliability of the design. The native intra-HD can be reduced to 0.06% with 17 mV of thresholding with only 4% of the total combinations discarded. To the best our knowledge, this is also the first demonstration of photonic crystals and an optical PUF in CMOS.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- CMOS imager
- Chip identification
- optical physically unclonable functions (PUFs)
- photonic crystals
- process variations