CMOS logic design with independent-gate FinFETs

Anish Muttreja; Niket Agarwal; Niraj K. Jha

doi:10.1109/ICCD.2007.4601953

CMOS logic design with independent-gate FinFETs

Anish Muttreja, Niket Agarwal, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

124 Scopus citations

Abstract

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logicstyle is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.

Original language	English (US)
Title of host publication	2007 IEEE International Conference on Computer Design, ICCD 2007
Pages	560-567
Number of pages	8
DOIs	https://doi.org/10.1109/ICCD.2007.4601953
State	Published - 2007
Event	2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States Duration: Oct 7 2007 → Oct 10 2007

Publication series

Name	2007 IEEE International Conference on Computer Design, ICCD 2007

Other

Other	2007 IEEE International Conference on Computer Design, ICCD 2007
Country/Territory	United States
City	Lake Tahoe, CA
Period	10/7/07 → 10/10/07

All Science Journal Classification (ASJC) codes

Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2007.4601953

Cite this

@inproceedings{37dc512e4f824602a104870ac3af1a73,

title = "CMOS logic design with independent-gate FinFETs",

abstract = "Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logicstyle is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.",

author = "Anish Muttreja and Niket Agarwal and Jha, {Niraj K.}",

year = "2007",

doi = "10.1109/ICCD.2007.4601953",

language = "English (US)",

isbn = "1424412587",

series = "2007 IEEE International Conference on Computer Design, ICCD 2007",

pages = "560--567",

booktitle = "2007 IEEE International Conference on Computer Design, ICCD 2007",

note = "2007 IEEE International Conference on Computer Design, ICCD 2007 ; Conference date: 07-10-2007 Through 10-10-2007",

}

Muttreja, A, Agarwal, N & Jha, NK 2007, CMOS logic design with independent-gate FinFETs. in 2007 IEEE International Conference on Computer Design, ICCD 2007., 4601953, 2007 IEEE International Conference on Computer Design, ICCD 2007, pp. 560-567, 2007 IEEE International Conference on Computer Design, ICCD 2007, Lake Tahoe, CA, United States, 10/7/07. https://doi.org/10.1109/ICCD.2007.4601953

TY - GEN

T1 - CMOS logic design with independent-gate FinFETs

AU - Muttreja, Anish

AU - Agarwal, Niket

AU - Jha, Niraj K.

PY - 2007

Y1 - 2007

N2 - Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logicstyle is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.

AB - Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logicstyle is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=47649083623&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=47649083623&partnerID=8YFLogxK

U2 - 10.1109/ICCD.2007.4601953

DO - 10.1109/ICCD.2007.4601953

M3 - Conference contribution

AN - SCOPUS:47649083623

SN - 1424412587

SN - 9781424412587

T3 - 2007 IEEE International Conference on Computer Design, ICCD 2007

SP - 560

EP - 567

BT - 2007 IEEE International Conference on Computer Design, ICCD 2007

T2 - 2007 IEEE International Conference on Computer Design, ICCD 2007

Y2 - 7 October 2007 through 10 October 2007

ER -

CMOS logic design with independent-gate FinFETs

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this