CMOS logic design with independent-gate FinFETs

Anish Muttreja, Niket Agarwal, Niraj Kumar Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

110 Scopus citations

Abstract

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device characteristics, high active leakage may remain a problem for FinFET logic circuits. Leakage is found to contribute 31.3% of total power consumption in power-optimized FinFET logic circuits. Various FinFET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logicstyle is presented. Leakage (total) power savings of 64.7% (14.5%) under tight delay constraints and 91.2% (37.2%) under relaxed delay constraints, through the judicious use of FinFET logic styles, are demonstrated.

Original languageEnglish (US)
Title of host publication2007 IEEE International Conference on Computer Design, ICCD 2007
Pages560-567
Number of pages8
DOIs
StatePublished - Dec 1 2007
Event2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States
Duration: Oct 7 2007Oct 10 2007

Publication series

Name2007 IEEE International Conference on Computer Design, ICCD 2007

Other

Other2007 IEEE International Conference on Computer Design, ICCD 2007
CountryUnited States
CityLake Tahoe, CA
Period10/7/0710/10/07

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Muttreja, A., Agarwal, N., & Jha, N. K. (2007). CMOS logic design with independent-gate FinFETs. In 2007 IEEE International Conference on Computer Design, ICCD 2007 (pp. 560-567). [4601953] (2007 IEEE International Conference on Computer Design, ICCD 2007). https://doi.org/10.1109/ICCD.2007.4601953