Clock, flip-flop, and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology

Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to single event effects (SEE). The variables characterized included: well structure on the wafer, density of well contacts, logic data pattern, angle of indicence, flip-flop redundancy, variation in sensitive node spacing, and the effect of transients as a function of combinatorial logic type. Analysis of the cross section contribution from the clock, flip-flop and SET target circuitry showed that any hardening technique used in a production integrated circuit may be limited in its effectiveness due to other circuits and logic in the integrated circuit.