Clock, flip-flop, and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology

David L. Hansen, Eric J. Miller, Aj Kleinosowski, Kirk Kohnen, Anthony Le, Dick Wong, Karina Amador, Mark Baze, David DeSalvo, Maryanne Dooley, Kenneth Gerst, Barrie Hughlock, Bradford Jeppson, R. D. Jobe, David Nardi, Isabel Ojalvo, Brad Rasmussen, David Sunderland, John Truong, Michael YooE. Zayas

Research output: Contribution to journalArticlepeer-review

34 Scopus citations


Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to single event effects (SEE). The variables characterized included: well structure on the wafer, density of well contacts, logic data pattern, angle of indicence, flip-flop redundancy, variation in sensitive node spacing, and the effect of transients as a function of combinatorial logic type. Analysis of the cross section contribution from the clock, flip-flop and SET target circuitry showed that any hardening technique used in a production integrated circuit may be limited in its effectiveness due to other circuits and logic in the integrated circuit.

Original languageEnglish (US)
Article number5341352
Pages (from-to)3542-3550
Number of pages9
JournalIEEE Transactions on Nuclear Science
Issue number6
StatePublished - Dec 2009
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Nuclear and High Energy Physics
  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering


  • Heavy ion
  • Rad-hard by design
  • Single event upset


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