Clock, flip-flop, and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology

David L. Hansen; Eric J. Miller; Aj Kleinosowski; Kirk Kohnen; Anthony Le; Dick Wong; Karina Amador; Mark Baze; David DeSalvo; Maryanne Dooley; Kenneth Gerst; Barrie Hughlock; Bradford Jeppson; R. D. Jobe; David Nardi; Isabel Ojalvo; Brad Rasmussen; David Sunderland; John Truong; Michael Yoo; E. Zayas

doi:10.1109/TNS.2009.2031972

Clock, flip-flop, and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology

David L. Hansen, Eric J. Miller, Aj Kleinosowski, Kirk Kohnen, Anthony Le, Dick Wong, Karina Amador, Mark Baze, David DeSalvo, Maryanne Dooley, Kenneth Gerst, Barrie Hughlock, Bradford Jeppson, R. D. Jobe, David Nardi, Isabel Ojalvo, Brad Rasmussen, David Sunderland, John Truong, Michael YooE. Zayas

Research output: Contribution to journal › Article › peer-review

35 Scopus citations

Abstract

Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to single event effects (SEE). The variables characterized included: well structure on the wafer, density of well contacts, logic data pattern, angle of indicence, flip-flop redundancy, variation in sensitive node spacing, and the effect of transients as a function of combinatorial logic type. Analysis of the cross section contribution from the clock, flip-flop and SET target circuitry showed that any hardening technique used in a production integrated circuit may be limited in its effectiveness due to other circuits and logic in the integrated circuit.

Original language	English (US)
Article number	5341352
Pages (from-to)	3542-3550
Number of pages	9
Journal	IEEE Transactions on Nuclear Science
Volume	56
Issue number	6
DOIs	https://doi.org/10.1109/TNS.2009.2031972
State	Published - Dec 2009
Externally published	Yes

All Science Journal Classification (ASJC) codes

Nuclear and High Energy Physics
Nuclear Energy and Engineering
Electrical and Electronic Engineering

Keywords

Heavy ion
Rad-hard by design
Single event upset

Access to Document

10.1109/TNS.2009.2031972

Cite this

Hansen, D. L., Miller, E. J., Kleinosowski, A., Kohnen, K., Le, A., Wong, D., Amador, K., Baze, M., DeSalvo, D., Dooley, M., Gerst, K., Hughlock, B., Jeppson, B., Jobe, R. D., Nardi, D., Ojalvo, I., Rasmussen, B., Sunderland, D., Truong, J., ... Zayas, E. (2009). Clock, flip-flop, and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology. IEEE Transactions on Nuclear Science, 56(6), 3542-3550. Article 5341352. https://doi.org/10.1109/TNS.2009.2031972

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title = "Clock, flip-flop, and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology",

abstract = "Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to single event effects (SEE). The variables characterized included: well structure on the wafer, density of well contacts, logic data pattern, angle of indicence, flip-flop redundancy, variation in sensitive node spacing, and the effect of transients as a function of combinatorial logic type. Analysis of the cross section contribution from the clock, flip-flop and SET target circuitry showed that any hardening technique used in a production integrated circuit may be limited in its effectiveness due to other circuits and logic in the integrated circuit.",

keywords = "Heavy ion, Rad-hard by design, Single event upset",

author = "Hansen, {David L.} and Miller, {Eric J.} and Aj Kleinosowski and Kirk Kohnen and Anthony Le and Dick Wong and Karina Amador and Mark Baze and David DeSalvo and Maryanne Dooley and Kenneth Gerst and Barrie Hughlock and Bradford Jeppson and Jobe, {R. D.} and David Nardi and Isabel Ojalvo and Brad Rasmussen and David Sunderland and John Truong and Michael Yoo and E. Zayas",

year = "2009",

month = dec,

doi = "10.1109/TNS.2009.2031972",

language = "English (US)",

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Hansen, DL, Miller, EJ, Kleinosowski, A, Kohnen, K, Le, A, Wong, D, Amador, K, Baze, M, DeSalvo, D, Dooley, M, Gerst, K, Hughlock, B, Jeppson, B, Jobe, RD, Nardi, D, Ojalvo, I, Rasmussen, B, Sunderland, D, Truong, J, Yoo, M & Zayas, E 2009, 'Clock, flip-flop, and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology', IEEE Transactions on Nuclear Science, vol. 56, no. 6, 5341352, pp. 3542-3550. https://doi.org/10.1109/TNS.2009.2031972

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AU - Hansen, David L.

AU - Miller, Eric J.

AU - Kleinosowski, Aj

AU - Kohnen, Kirk

AU - Le, Anthony

AU - Wong, Dick

AU - Amador, Karina

AU - Baze, Mark

AU - DeSalvo, David

AU - Dooley, Maryanne

AU - Gerst, Kenneth

AU - Hughlock, Barrie

AU - Jeppson, Bradford

AU - Jobe, R. D.

AU - Nardi, David

AU - Ojalvo, Isabel

AU - Rasmussen, Brad

AU - Sunderland, David

AU - Truong, John

AU - Yoo, Michael

AU - Zayas, E.

PY - 2009/12

Y1 - 2009/12

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AB - Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to single event effects (SEE). The variables characterized included: well structure on the wafer, density of well contacts, logic data pattern, angle of indicence, flip-flop redundancy, variation in sensitive node spacing, and the effect of transients as a function of combinatorial logic type. Analysis of the cross section contribution from the clock, flip-flop and SET target circuitry showed that any hardening technique used in a production integrated circuit may be limited in its effectiveness due to other circuits and logic in the integrated circuit.

KW - Heavy ion

KW - Rad-hard by design

KW - Single event upset

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Clock, flip-flop, and combinatorial logic contributions to the SEU cross section in 90 nm ASIC technology

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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