CIFER: A Cache-Coherent 12-nm 16-mm2SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2Synthesizable eFPGA

Ang Li, Ting Jung Chang, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

This letter presents CIFER, the world's first open-source, fully cache-coherent, heterogeneous many-core, CPU-FPGA system-on-chips. The 12 nm, 16-mm2 chip integrates four 64-bit, OS-capable, RISC-V application cores; three TinyCore clusters that each contain six 32-bit, RISC-V compute cores (18 in total); and an electronic design automation-synthesized, standard-cell-based eFPGA. CIFER enables the decomposition of real-world applications and tailored execution (parallelization or specialization) per decomposed task. Our evaluation shows that: 1) the TinyCore clusters increase the throughput and energy efficiency of data- and thread-parallel tasks by up to 7.95× and 7.75× over one 64-bit core, respectively; 2) the eFPGA increases the throughput and energy efficiency of hardware-accelerable tasks by up to 9.29× and 10.62× , respectively; and 3) using coherent caches for data transfer between the processors and the eFPGA increases the throughput and energy efficiency by up to 11.1× and 10.5× , respectively.

Original languageEnglish (US)
Pages (from-to)229-232
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume6
DOIs
StatePublished - 2023

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Keywords

  • Cache memory
  • computer architecture
  • parallel architectures
  • programmable logic arrays
  • reconfigurable architectures
  • system-on-chip (SoC)

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