How do we design an error correcting code and a corresponding decoding implementation to minimize not just the transmit power, but the sum of transmit and decoding power? Recent interest in this question has led to new fundamental results that show the traditional approach of designing the code and the decoder implementation in isolation can be suboptimal. However, joint design of codes and their corresponding decoder implementations can be hard simply because of the sheer number of possibilities for both, and the human effort often required in optimizing the decoder implementation for a given code. In this paper, we suggest taking a middle-path between analyzing theoretical models of decoding and building decoder implementations. Based on circuit simulations of power consumption of decoders for simple regular LDPC codes, we develop circuit models for the decoding power for larger and more complex (but still regular) LDPC codes. These models are then used to search for the best code and corresponding decoder (within a limited set) for a given communication distance and error probability.