TY - GEN
T1 - Choosing 'green' codes by simulation-based modeling of implementations
AU - Ganesan, Karthik
AU - Wen, Yang
AU - Grover, Pulkit
AU - Goldsmith, Andrea
AU - Rabaey, Jan
PY - 2012
Y1 - 2012
N2 - How do we design an error correcting code and a corresponding decoding implementation to minimize not just the transmit power, but the sum of transmit and decoding power? Recent interest in this question has led to new fundamental results that show the traditional approach of designing the code and the decoder implementation in isolation can be suboptimal. However, joint design of codes and their corresponding decoder implementations can be hard simply because of the sheer number of possibilities for both, and the human effort often required in optimizing the decoder implementation for a given code. In this paper, we suggest taking a middle-path between analyzing theoretical models of decoding and building decoder implementations. Based on circuit simulations of power consumption of decoders for simple regular LDPC codes, we develop circuit models for the decoding power for larger and more complex (but still regular) LDPC codes. These models are then used to search for the best code and corresponding decoder (within a limited set) for a given communication distance and error probability.
AB - How do we design an error correcting code and a corresponding decoding implementation to minimize not just the transmit power, but the sum of transmit and decoding power? Recent interest in this question has led to new fundamental results that show the traditional approach of designing the code and the decoder implementation in isolation can be suboptimal. However, joint design of codes and their corresponding decoder implementations can be hard simply because of the sheer number of possibilities for both, and the human effort often required in optimizing the decoder implementation for a given code. In this paper, we suggest taking a middle-path between analyzing theoretical models of decoding and building decoder implementations. Based on circuit simulations of power consumption of decoders for simple regular LDPC codes, we develop circuit models for the decoding power for larger and more complex (but still regular) LDPC codes. These models are then used to search for the best code and corresponding decoder (within a limited set) for a given communication distance and error probability.
KW - Joint design of codes and decoders
KW - circuit models for decoding power
KW - iterative message-passing decoding
KW - low-density parity-check (LDPC) codes
KW - system-level power consumption
UR - http://www.scopus.com/inward/record.url?scp=84877650137&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84877650137&partnerID=8YFLogxK
U2 - 10.1109/GLOCOM.2012.6503621
DO - 10.1109/GLOCOM.2012.6503621
M3 - Conference contribution
AN - SCOPUS:84877650137
SN - 9781467309219
T3 - Proceedings - IEEE Global Communications Conference, GLOBECOM
SP - 3286
EP - 3292
BT - 2012 IEEE Global Communications Conference, GLOBECOM 2012
T2 - 2012 IEEE Global Communications Conference, GLOBECOM 2012
Y2 - 3 December 2012 through 7 December 2012
ER -