Chemical vapor deposition epitaxy of silicon and silicon-carbon alloys at high rates and low temperatures using neopentasilane

J. C. Sturm, K. H. Chung, N. Yao, E. Sanchez, K. K. Singh, D. Carlson, S. Kuppurao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

The silicon precursor neopentasilane is used to grow epitaxial silicon at high growth rates from 550 to 700°C, with rates over 100 nm/min achieved at 600°C. The layer quality as observed by TEM and the performance of FET's made in these films is high. Neopentasilane has also been used to grow dilute strained Si1-yCy alloys on silicon with very high growth rates. For carbon levels on the order of 2%, strained layers were grown at rates over 40 nm/min.

Original languageEnglish (US)
Title of host publicationECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS
Subtitle of host publicationNew Materials, Processes and Equipment, 3
Pages429-436
Number of pages8
Edition1
DOIs
StatePublished - Dec 1 2007
EventInternational Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting - Chicago, IL, United States
Duration: May 6 2007May 10 2007

Publication series

NameECS Transactions
Number1
Volume6
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherInternational Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting
CountryUnited States
CityChicago, IL
Period5/6/075/10/07

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Sturm, J. C., Chung, K. H., Yao, N., Sanchez, E., Singh, K. K., Carlson, D., & Kuppurao, S. (2007). Chemical vapor deposition epitaxy of silicon and silicon-carbon alloys at high rates and low temperatures using neopentasilane. In ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 (1 ed., pp. 429-436). (ECS Transactions; Vol. 6, No. 1). https://doi.org/10.1149/1.2727429