Characterizing the TLB behavior of emerging parallelworkloads on chip multiprocessors

Abhishek Bhattacharjee, Margaret Rose Martonosi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

64 Scopus citations

Abstract

Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TLB designs to lower access times and miss rates; these, however, have been targeted towards uniprocessor architectures. As the computer industry embraces chip multiprocessor (CMP) architectures, it is important to study the TLB behavior of emerging parallel workloads. This work presents the first full-system characterization of the TLB behavior of emerging parallel applications on real-system CMPs. Using the PARSEC benchmarks, representative of emerging RMS workloads, we show that TLB misses can hinder system performance significantly. We also evaluate TLB miss stream patterns and show that multiple threads of a parallel execution experience a large number of redundant and predictable misses. For our evaluated benchmarks, 30% to 95% of the total misses fall under this category. Our results point to the need for novel TLB designs encouraging inter-core cooperation, either through hierarchically shared TLBs or through inter-core TLB prediction mechanisms.

Original languageEnglish (US)
Title of host publicationProceedings - 2009 18th International Conference on Parallel Architectures and Compilation Techniques, PACT 2009
Pages29-40
Number of pages12
DOIs
StatePublished - 2009
Event2009 18th International Conference on Parallel Architectures and Compilation Techniques, PACT 2009 - Raleigh, NC, United States
Duration: Sep 12 2009Sep 16 2009

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)1089-795X

Other

Other2009 18th International Conference on Parallel Architectures and Compilation Techniques, PACT 2009
CountryUnited States
CityRaleigh, NC
Period9/12/099/16/09

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Characterizing the TLB behavior of emerging parallelworkloads on chip multiprocessors'. Together they form a unique fingerprint.

Cite this