Certified Timing Verification and the Transition Delay of a Logic Circuit

Srinivas Devadas; Kurt Keutzer; Albert Wang; Sharad Malik

doi:10.1109/92.311642

Certified Timing Verification and the Transition Delay of a Logic Circuit

Srinivas Devadas, Kurt Keutzer, Albert Wang, Sharad Malik

Research output: Contribution to journal › Article › peer-review

11 Scopus citations

Abstract

Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.

Original language	English (US)
Pages (from-to)	333-342
Number of pages	10
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	2
Issue number	3
DOIs	https://doi.org/10.1109/92.311642
State	Published - Sep 1994

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/92.311642

Cite this

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title = "Certified Timing Verification and the Transition Delay of a Logic Circuit",

abstract = "Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.",

author = "Srinivas Devadas and Kurt Keutzer and Albert Wang and Sharad Malik",

note = "Funding Information: Manuscript received July 6, 1993; revised February 2, 1994 and March 16, 1994. This work was supported in part by the Defense Advanced Research Projects Agency under Contract {"}14-91-5-1968 and in part by a NSF Young Investigator Award with matching funds from Mitsubishi and IBM Corporation. S. Devadas is with the Department of EECS, Massachusetts Institute of Technology, Cambridge, MA 02139 USA. K. Keutzer and A. Wang are with Synopsys, Inc., Mountain View, CA USA. S. Malik is with the Department of Electronic Engineering, Princeton University, Princeton, NJ 08540 USA. IEEE Log Number 9403168.",

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AU - Devadas, Srinivas

AU - Keutzer, Kurt

AU - Wang, Albert

AU - Malik, Sharad

N1 - Funding Information: Manuscript received July 6, 1993; revised February 2, 1994 and March 16, 1994. This work was supported in part by the Defense Advanced Research Projects Agency under Contract "14-91-5-1968 and in part by a NSF Young Investigator Award with matching funds from Mitsubishi and IBM Corporation. S. Devadas is with the Department of EECS, Massachusetts Institute of Technology, Cambridge, MA 02139 USA. K. Keutzer and A. Wang are with Synopsys, Inc., Mountain View, CA USA. S. Malik is with the Department of Electronic Engineering, Princeton University, Princeton, NJ 08540 USA. IEEE Log Number 9403168.

PY - 1994/9

Y1 - 1994/9

N2 - Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.

AB - Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.

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Certified Timing Verification and the Transition Delay of a Logic Circuit

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