Certified Timing Verification and the Transition Delay of a Logic Circuit

Srinivas Devadas, Kurt Keutzer, Albert Wang, Sharad Malik

Research output: Contribution to journalArticle

9 Scopus citations

Abstract

Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.

Original languageEnglish (US)
Pages (from-to)333-342
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume2
Issue number3
DOIs
StatePublished - Sep 1994

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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