Certified timing verification and the transition delay of a logic circuit

Srinivas Devadas; Kurt Keutzer; Sharad Malik; Albert Wang

Certified timing verification and the transition delay of a logic circuit

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multi-vector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.

Original language	English (US)
Title of host publication	Proceedings - Design Automation Conference
Publisher	Publ by IEEE
Pages	549-555
Number of pages	7
ISBN (Print)	0818628227
State	Published - Dec 1 1992
Externally published	Yes
Event	Proceedings of the 29th ACM/IEEE Design Automation Conference - Anaheim, CA, USA Duration: Jun 8 1992 → Jun 12 1992

Other

Other	Proceedings of the 29th ACM/IEEE Design Automation Conference
City	Anaheim, CA, USA
Period	6/8/92 → 6/12/92

All Science Journal Classification (ASJC) codes

Engineering(all)

Cite this

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title = "Certified timing verification and the transition delay of a logic circuit",

abstract = "Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multi-vector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.",

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note = "Proceedings of the 29th ACM/IEEE Design Automation Conference ; Conference date: 08-06-1992 Through 12-06-1992",

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AU - Devadas, Srinivas

AU - Keutzer, Kurt

AU - Malik, Sharad

AU - Wang, Albert

PY - 1992/12/1

Y1 - 1992/12/1

N2 - Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multi-vector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.

AB - Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multi-vector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.

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M3 - Conference contribution

AN - SCOPUS:0026981958

SN - 0818628227

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BT - Proceedings - Design Automation Conference

PB - Publ by IEEE

T2 - Proceedings of the 29th ACM/IEEE Design Automation Conference

Y2 - 8 June 1992 through 12 June 1992

ER -

Certified timing verification and the transition delay of a logic circuit

Abstract

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All Science Journal Classification (ASJC) codes

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