Abstract
Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multi-vector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.
Original language | English (US) |
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Title of host publication | Proceedings - Design Automation Conference |
Publisher | Publ by IEEE |
Pages | 549-555 |
Number of pages | 7 |
ISBN (Print) | 0818628227 |
State | Published - Dec 1 1992 |
Externally published | Yes |
Event | Proceedings of the 29th ACM/IEEE Design Automation Conference - Anaheim, CA, USA Duration: Jun 8 1992 → Jun 12 1992 |
Other
Other | Proceedings of the 29th ACM/IEEE Design Automation Conference |
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City | Anaheim, CA, USA |
Period | 6/8/92 → 6/12/92 |
All Science Journal Classification (ASJC) codes
- Engineering(all)