Certified timing verification and the transition delay of a logic circuit

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations

Abstract

Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multi-vector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Pages549-555
Number of pages7
ISBN (Print)0818628227
StatePublished - Dec 1 1992
Externally publishedYes
EventProceedings of the 29th ACM/IEEE Design Automation Conference - Anaheim, CA, USA
Duration: Jun 8 1992Jun 12 1992

Other

OtherProceedings of the 29th ACM/IEEE Design Automation Conference
CityAnaheim, CA, USA
Period6/8/926/12/92

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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