@inproceedings{a27d19e55b9f418a8958a756e625d722,
title = "Certified timing verification and the transition delay of a logic circuit",
abstract = "Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multi-vector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.",
author = "Srinivas Devadas and Kurt Keutzer and Sharad Malik and Albert Wang",
year = "1992",
language = "English (US)",
isbn = "0818628227",
series = "Proceedings - Design Automation Conference",
publisher = "Publ by IEEE",
pages = "549--555",
booktitle = "Proceedings - Design Automation Conference",
note = "Proceedings of the 29th ACM/IEEE Design Automation Conference ; Conference date: 08-06-1992 Through 12-06-1992",
}