Carrier confinement in MOS-gated GexSi1-x/Si heterostructures

P. M. Garone, V. Venkataraman, James Christopher Sturm

Research output: Contribution to journalArticle

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Abstract

The confinement of carriers in a MOS-gated GexSi1-x heterostructure is numerically modeled and experimentally confirmed. The structure, which may be useful for improved pMOS device performance, uses a MOS gate to modulate the hole density at a buried Si/GexSi1-x interface. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structure design, and clear experimental evidence for such carrier confinement is given. Simulations have shown that it is desirable to use a minimal Si buffer thickness and a maximum Ge fraction to maximize the number of holes confined in the GexSi1-x well, subject to the constraints of surface scattering and processing considerations.

Original languageEnglish (US)
Pages (from-to)383-386
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - Dec 1 1990

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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