TY - JOUR
T1 - Carrier confinement in MOS-gated GexSi1-x/Si heterostructures
AU - Garone, P. M.
AU - Venkataraman, V.
AU - Sturm, James Christopher
PY - 1990/12/1
Y1 - 1990/12/1
N2 - The confinement of carriers in a MOS-gated GexSi1-x heterostructure is numerically modeled and experimentally confirmed. The structure, which may be useful for improved pMOS device performance, uses a MOS gate to modulate the hole density at a buried Si/GexSi1-x interface. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structure design, and clear experimental evidence for such carrier confinement is given. Simulations have shown that it is desirable to use a minimal Si buffer thickness and a maximum Ge fraction to maximize the number of holes confined in the GexSi1-x well, subject to the constraints of surface scattering and processing considerations.
AB - The confinement of carriers in a MOS-gated GexSi1-x heterostructure is numerically modeled and experimentally confirmed. The structure, which may be useful for improved pMOS device performance, uses a MOS gate to modulate the hole density at a buried Si/GexSi1-x interface. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structure design, and clear experimental evidence for such carrier confinement is given. Simulations have shown that it is desirable to use a minimal Si buffer thickness and a maximum Ge fraction to maximize the number of holes confined in the GexSi1-x well, subject to the constraints of surface scattering and processing considerations.
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M3 - Article
AN - SCOPUS:0025577495
SN - 0163-1918
SP - 383
EP - 386
JO - Technical Digest - International Electron Devices Meeting
JF - Technical Digest - International Electron Devices Meeting
ER -