Carrier confinement in MOS-gated Ge_xSi_1-x/Si heterostructures

Keyphrases

• Heterostructure 100%
• Carrier Confinement 100%
• Device Performance 50%
• Hole Density 50%
• Numerical Modeling 50%
• Surface Processing 50%
• Surface Scattering 50%
• Structure Design 50%
• Ge Fraction 50%
• Buffer Size 50%
• PMOS Device 50%
• Number of Holes 50%

Material Science

• Heterojunction 100%
• Density 50%