Carrier confinement in MOS-gated GexSi1-x/Si heterostructures

P. M. Garone; V. Venkataraman; J. C. Sturm

Carrier confinement in MOS-gated Ge_xSi_1-x/Si heterostructures

P. M. Garone, V. Venkataraman, J. C. Sturm

Research output: Contribution to journal › Conference article › peer-review

Abstract

The confinement of carriers in a MOS-gated Ge_xSi_1-x heterostructure is numerically modeled and experimentally confirmed. The structure, which may be useful for improved pMOS device performance, uses a MOS gate to modulate the hole density at a buried Si/Ge_xSi_1-x interface. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structure design, and clear experimental evidence for such carrier confinement is given. Simulations have shown that it is desirable to use a minimal Si buffer thickness and a maximum Ge fraction to maximize the number of holes confined in the Ge_xSi_1-x well, subject to the constraints of surface scattering and processing considerations.

Original language	English (US)
Pages (from-to)	383-386
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
State	Published - Dec 1990
Event	1990 International Electron Devices Meeting - San Francisco, CA, USA Duration: Dec 9 1990 → Dec 12 1990

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Materials Chemistry
Electrical and Electronic Engineering

Cite this

@article{e8f78b1ccfbb422b931ef81186b7fe7c,

title = "Carrier confinement in MOS-gated GexSi1-x/Si heterostructures",

abstract = "The confinement of carriers in a MOS-gated GexSi1-x heterostructure is numerically modeled and experimentally confirmed. The structure, which may be useful for improved pMOS device performance, uses a MOS gate to modulate the hole density at a buried Si/GexSi1-x interface. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structure design, and clear experimental evidence for such carrier confinement is given. Simulations have shown that it is desirable to use a minimal Si buffer thickness and a maximum Ge fraction to maximize the number of holes confined in the GexSi1-x well, subject to the constraints of surface scattering and processing considerations.",

author = "Garone, {P. M.} and V. Venkataraman and Sturm, {J. C.}",

year = "1990",

month = dec,

language = "English (US)",

pages = "383--386",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "1990 International Electron Devices Meeting ; Conference date: 09-12-1990 Through 12-12-1990",

}

TY - JOUR

T1 - Carrier confinement in MOS-gated GexSi1-x/Si heterostructures

AU - Garone, P. M.

AU - Venkataraman, V.

AU - Sturm, J. C.

PY - 1990/12

Y1 - 1990/12

N2 - The confinement of carriers in a MOS-gated GexSi1-x heterostructure is numerically modeled and experimentally confirmed. The structure, which may be useful for improved pMOS device performance, uses a MOS gate to modulate the hole density at a buried Si/GexSi1-x interface. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structure design, and clear experimental evidence for such carrier confinement is given. Simulations have shown that it is desirable to use a minimal Si buffer thickness and a maximum Ge fraction to maximize the number of holes confined in the GexSi1-x well, subject to the constraints of surface scattering and processing considerations.

AB - The confinement of carriers in a MOS-gated GexSi1-x heterostructure is numerically modeled and experimentally confirmed. The structure, which may be useful for improved pMOS device performance, uses a MOS gate to modulate the hole density at a buried Si/GexSi1-x interface. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structure design, and clear experimental evidence for such carrier confinement is given. Simulations have shown that it is desirable to use a minimal Si buffer thickness and a maximum Ge fraction to maximize the number of holes confined in the GexSi1-x well, subject to the constraints of surface scattering and processing considerations.

UR - http://www.scopus.com/inward/record.url?scp=0025577495&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025577495&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0025577495

SN - 0163-1918

SP - 383

EP - 386

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 1990 International Electron Devices Meeting

Y2 - 9 December 1990 through 12 December 1990

ER -

Carrier confinement in MOS-gated Ge_xSi_1-x/Si heterostructures

Abstract

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this