CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations

Chun Yi Lee, Niraj Kumar Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

We present CACTI-FinFET, an integrated framework for simulation of power, delay, temperature, as well as process variations of FinFET-based caches. We have developed a FinFET design library and process variation models to characterize the delay and leakage spreads of such caches. We present results for various FinFET design styles and show that mixing different design styles may be a promising strategy for optimizing cache delay and leakage.

Original languageEnglish (US)
Title of host publication2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
Pages866-871
Number of pages6
StatePublished - Sep 16 2011
Event2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 - San Diego, CA, United States
Duration: Jun 5 2011Jun 9 2011

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
CountryUnited States
CitySan Diego, CA
Period6/5/116/9/11

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Keywords

  • CACTI-FinFET
  • FinFETs
  • cache simulator
  • process variation

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    Lee, C. Y., & Jha, N. K. (2011). CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations. In 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 (pp. 866-871). [5982007] (Proceedings - Design Automation Conference).