Cache modeling for real-time software: Beyond direct mapped instruction caches

Yau Tsun Steven Li, Sharad Malik, Andrew Wolfe

Research output: Contribution to conferencePaper

145 Scopus citations

Abstract

This paper presents a method for determining a tight bound on the worst case execution time of a program when running on a given hardware system with cache memory. Caches are used to improve the average memory performance - however, their presence complicates the worst case timing analysis. Any pessimistic predictions on cache hits/misses will result in loose estimation. In our previous research in this area, we built an Integer-Linear-Programming solution for this problem which included analysis of direct mapped instruction caches. In this paper, we describe the complex extensions of this technique to deal with set associative instruction caches, data caches and unified caches. We believe that this research now provides a comprehensive solution to the problem of worst-case performance analysis of software running on processors with caches. These techniques have been implemented in a design tool cinderella. Some experimental results are presented that demonstrate the practical applicability of this analysis.

Original languageEnglish (US)
Pages254-263
Number of pages10
StatePublished - Dec 1 1996
EventProceedings of the 1996 17th IEEE Real-Time Systems Symposium - Washington, DC, USA
Duration: Dec 4 1996Dec 6 1996

Other

OtherProceedings of the 1996 17th IEEE Real-Time Systems Symposium
CityWashington, DC, USA
Period12/4/9612/6/96

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

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    Li, Y. T. S., Malik, S., & Wolfe, A. (1996). Cache modeling for real-time software: Beyond direct mapped instruction caches. 254-263. Paper presented at Proceedings of the 1996 17th IEEE Real-Time Systems Symposium, Washington, DC, USA, .