TY - GEN
T1 - Cache coherence for shared memory multiprocessors based on virtual memory support
AU - Petersen, K.
AU - Li, Kai
N1 - Funding Information:
This research was supported in part by NSF grant CCR-!)02089:3, by DAHF’A and ONR under contracts N00014-91-J- 4039, and by Intel Supercomputer Systems Division. We thank Mark (ireenstreet, Jim Plank, Anne Rogers, and the reviewers for their careful conunents on earlier drafts of this paper.
Publisher Copyright:
© 1993 IEEE.
PY - 1993
Y1 - 1993
N2 - This paper presents a software cache coherence scheme that uses virtual memory (VM) support to maintain cache coherency for shared memory multiprocessors. Traditional VM translation hardware in each processor is used to detect memory access attempts that would violate cache coherence and system software is used to enforce coherence. The implementation of this class of coherence schemes is very economical: it requires neither special multiprocessor hardware nor compiler support, and easily incorporates different consistency models. The authors evaluated two consistency models for the VM-based approach: sequential consistency and lazy release consistency. The VM-based schemes are compared with a bus based snoopy caching architecture, and the authors' trace-driven simulation results show that the VM-based cache coherence schemes are practical for small-scale, shared memory multiprocessors.
AB - This paper presents a software cache coherence scheme that uses virtual memory (VM) support to maintain cache coherency for shared memory multiprocessors. Traditional VM translation hardware in each processor is used to detect memory access attempts that would violate cache coherence and system software is used to enforce coherence. The implementation of this class of coherence schemes is very economical: it requires neither special multiprocessor hardware nor compiler support, and easily incorporates different consistency models. The authors evaluated two consistency models for the VM-based approach: sequential consistency and lazy release consistency. The VM-based schemes are compared with a bus based snoopy caching architecture, and the authors' trace-driven simulation results show that the VM-based cache coherence schemes are practical for small-scale, shared memory multiprocessors.
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U2 - 10.1109/IPPS.1993.262854
DO - 10.1109/IPPS.1993.262854
M3 - Conference contribution
AN - SCOPUS:85013507736
T3 - Proceedings of 7th International Parallel Processing Symposium, IPPS 1993
SP - 49
EP - 55
BT - Proceedings of 7th International Parallel Processing Symposium, IPPS 1993
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th International Parallel Processing Symposium, IPPS 1993
Y2 - 13 April 1993 through 16 April 1993
ER -