Butterfly and inverse butterfly nets integration on Altera NIOS-II embedded processor

G. C. Cardarilli, L. Di Nunzio, R. Fazzolari, M. Re, Ruby B. Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

The Instruction Set Architecure (ISA) of micro-processors is usually word oriented, so it is not optimized to perform bit level operations. A functional unit oriented to the bit manipulation could accelerate the computation increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the integration between the Bit Manipulation Unit (BMU) described in [1], [2] and the Altera NIOS-II processor [5]. The BMU, described in VHDL, has been integrated in the processor using the Custom Logic feature [6] and implemented on an Altera-Stratix FPGA.

Original languageEnglish (US)
Title of host publicationConference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010
Pages1279-1283
Number of pages5
DOIs
StatePublished - Dec 1 2010
Event44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010 - Pacific Grove, CA, United States
Duration: Nov 7 2010Nov 10 2010

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Other

Other44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010
CountryUnited States
CityPacific Grove, CA
Period11/7/1011/10/10

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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    Cardarilli, G. C., Di Nunzio, L., Fazzolari, R., Re, M., & Lee, R. B. (2010). Butterfly and inverse butterfly nets integration on Altera NIOS-II embedded processor. In Conference Record of the 44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010 (pp. 1279-1283). [5757737] (Conference Record - Asilomar Conference on Signals, Systems and Computers). https://doi.org/10.1109/ACSSC.2010.5757737