Bundled execution of recurring traces for energy-efficient general purpose processing

Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott Mahlke, David I. August

Research output: Chapter in Book/Report/Conference proceedingConference contribution

84 Scopus citations


Technology scaling has delivered on its promises of increasing device density on a single chip. However, the voltage scaling trend has failed to keep up, introducing tight power constraints on manufactured parts. In such a scenario, there is a need to incorporate energy-efficient processing resources that can enable more computation within the same power budget. Energy efficiency solutions in the past have typically relied on application specific hardware and accelerators. Unfortunately, these approaches do not extend to general purpose applications due to their irregular and diverse code base. Towards this end, we propose BERET, an energy-efficient co-processor that can be configured to benefit a wide range of applications. Our approach identifies recurring instruction sequences as phases of "temporal regularity" in a program's execution, and maps suitable ones to the BERET hardware, a three-stage pipeline with a bundled execution model. This judicious off-loading of program execution to a reduced-complexity hardware demonstrates significant savings on instruction fetch, decode and register file accesses energy. On average, BERET reduces energy consumption by a factor of 3-4X for the program regions selected across a range of general-purpose and media applications. The average energy savings for the entire application run was 35% over a single-issue in-order processor.

Original languageEnglish (US)
Title of host publicationMICRO 44 - Proceedings of the 44th Annual IEEE/ACM Symposium on Microarchitecture
Number of pages12
StatePublished - 2011
Event44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44 - Porto Alegre, RS, Brazil
Duration: Dec 4 2011Dec 7 2011

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451


Other44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44
CityPorto Alegre, RS

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


  • co-processor
  • efficiency
  • energy saving
  • microarchitecture


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