Building a verification test plan: Trading brute force for finesse

Francine Bacchini; Sharad Malik; J. Bergeron; H. Foster; A. Piziali; R. S. Mitra; C. Ahlschlager; D. Stein

doi:10.1145/1146909.1147113

Building a verification test plan: Trading brute force for finesse

Francine Bacchini, Sharad Malik, J. Bergeron, H. Foster, A. Piziali, R. S. Mitra, C. Ahlschlager, D. Stein

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English (US)
Title of host publication	2006 43rd ACM/IEEE Design Automation Conference, DAC'06
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	805-806
Number of pages	2
ISBN (Print)	1595933816, 1595933816, 9781595933812
DOIs	https://doi.org/10.1145/1146909.1147113
State	Published - 2006
Event	43rd Annual Design Automation Conference, DAC 2006 - San Francisco, CA, United States Duration: Jul 24 2006 → Jul 28 2006

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	43rd Annual Design Automation Conference, DAC 2006
Country/Territory	United States
City	San Francisco, CA
Period	7/24/06 → 7/28/06

All Science Journal Classification (ASJC) codes

Control and Systems Engineering
Hardware and Architecture

Keywords

Coverage
Design verification
Formal verification
Functional simulation
Verification test plan

Access to Document

10.1145/1146909.1147113

Cite this

Bacchini, F., Malik, S., Bergeron, J., Foster, H., Piziali, A., Mitra, R. S., Ahlschlager, C., & Stein, D. (2006). Building a verification test plan: Trading brute force for finesse. In 2006 43rd ACM/IEEE Design Automation Conference, DAC'06 (pp. 805-806). (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1146909.1147113

@inproceedings{c93dc6bb52fd45709f8c113987c948d1,

title = "Building a verification test plan: Trading brute force for finesse",

keywords = "Coverage, Design verification, Formal verification, Functional simulation, Verification test plan",

author = "Francine Bacchini and Sharad Malik and J. Bergeron and H. Foster and A. Piziali and Mitra, {R. S.} and C. Ahlschlager and D. Stein",

year = "2006",

doi = "10.1145/1146909.1147113",

language = "English (US)",

isbn = "1595933816",

series = "Proceedings - Design Automation Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "805--806",

booktitle = "2006 43rd ACM/IEEE Design Automation Conference, DAC'06",

address = "United States",

note = "43rd Annual Design Automation Conference, DAC 2006 ; Conference date: 24-07-2006 Through 28-07-2006",

}

Bacchini, F, Malik, S, Bergeron, J, Foster, H, Piziali, A, Mitra, RS, Ahlschlager, C & Stein, D 2006, Building a verification test plan: Trading brute force for finesse. in 2006 43rd ACM/IEEE Design Automation Conference, DAC'06. Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., pp. 805-806, 43rd Annual Design Automation Conference, DAC 2006, San Francisco, CA, United States, 7/24/06. https://doi.org/10.1145/1146909.1147113

Building a verification test plan: Trading brute force for finesse. / Bacchini, Francine; Malik, Sharad; Bergeron, J. et al.
2006 43rd ACM/IEEE Design Automation Conference, DAC'06. Institute of Electrical and Electronics Engineers Inc., 2006. p. 805-806 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Building a verification test plan

T2 - 43rd Annual Design Automation Conference, DAC 2006

AU - Bacchini, Francine

AU - Malik, Sharad

AU - Bergeron, J.

AU - Foster, H.

AU - Piziali, A.

AU - Mitra, R. S.

AU - Ahlschlager, C.

AU - Stein, D.

PY - 2006

Y1 - 2006

KW - Coverage

KW - Design verification

KW - Formal verification

KW - Functional simulation

KW - Verification test plan

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U2 - 10.1145/1146909.1147113

DO - 10.1145/1146909.1147113

M3 - Conference contribution

AN - SCOPUS:34547166632

SN - 1595933816

SN - 9781595933812

T3 - Proceedings - Design Automation Conference

SP - 805

EP - 806

BT - 2006 43rd ACM/IEEE Design Automation Conference, DAC'06

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 24 July 2006 through 28 July 2006

ER -

Building a verification test plan: Trading brute force for finesse

Publication series

Conference

All Science Journal Classification (ASJC) codes

Keywords

Access to Document

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Cite this