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Bit level block matching systolic arrays
Yin Chan
,
S. Y. Kung
Electrical and Computer Engineering
Center for Statistics & Machine Learning
Research output
:
Contribution to journal
›
Conference article
›
peer-review
1
Scopus citations
Overview
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Dive into the research topics of 'Bit level block matching systolic arrays'. Together they form a unique fingerprint.
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Engineering
Block Level
100%
Systolic Arrays
100%
Hardware Complexity
50%
Dynamic Power Control
50%
Keyphrases
Bit Level
100%
Word-level
42%
Level Design
42%
Data Buffering
14%
Routing Area
14%
Application System
14%
Significant Bits
14%
Codec
14%
Bus Routing
14%
Picture Quality
14%
Dynamic Power Control
14%