Bit level block matching systolic arrays

In this paper, we present two bit-level systolic arrays for block matching which are designed by using a well-known methodology. Hardware complexities and speeds of both bit-level designs and conventional word-level arrays are compared by using synthesis tools. We pay special attention to a class of issues which were somewhat overlooked by previous publications, including power consumption due to high frequency, area due to routing and control, and optimal level of pipelining. Our design offers the following features: (1) The bit-level arrays are estimated to offer 200+% speed-up over word-level arrays, cf. Table 2. (2) When compared with word-level system with same throughput, the bit-level designs reduce control complexity, bus/routing area, and data buffering. (3) When dynamic power control is desired, these bit-level designs offer the flexibility of disabling some processing elements (for lower significant bits) at slight cost of picture quality. Finally, the potential promises and limitations of bit-level systolic block matching arrays, especially those concerning their integration into codec application system are investigated and discussed.