@inproceedings{0be755ab341f4b50a57025cecc125454,
title = "Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments",
abstract = "Behavioral synthesis tools which only optimize area and performance can easily produce a hard-to-test architecture. In this paper, we propose a new behavioral synthesis algorithm for testability which reduces sequential loop size while minimizing area. The algorithm considers two levels of testability synthesis;synthesis for non-scan, which assumes no test-strategy beforehand; and synthesis for partial scan, which uses the available scan information during resource allocation. Experimental results show that in almost all the cases our algorithm can synthesize benchmarks with a very high fault coverage in a small amount of test generation time, using the fewest registers and functional modules. Comparisons are also made with other behavioral synthesis algorithms which disregard testability in order to establish the efficacy of our approach.",
author = "Lee, {Tien Chien} and Jha, {Niraj K.} and Wolf, {Wayne H.}",
year = "1993",
doi = "10.1145/157485.164897",
language = "English (US)",
isbn = "0897915771",
series = "Proceedings - Design Automation Conference",
publisher = "Publ by IEEE",
pages = "292--297",
booktitle = "Proceedings - Design Automation Conference",
note = "Proceedings of the 30th ACM/IEEE Design Automation Conference ; Conference date: 14-06-1993 Through 18-06-1993",
}