Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments

Tien Chien Lee, Niraj K. Jha, Wayne H. Wolf

Research output: Chapter in Book/Report/Conference proceedingConference contribution

43 Scopus citations

Abstract

Behavioral synthesis tools which only optimize area and performance can easily produce a hard-to-test architecture. In this paper, we propose a new behavioral synthesis algorithm for testability which reduces sequential loop size while minimizing area. The algorithm considers two levels of testability synthesis;synthesis for non-scan, which assumes no test-strategy beforehand; and synthesis for partial scan, which uses the available scan information during resource allocation. Experimental results show that in almost all the cases our algorithm can synthesize benchmarks with a very high fault coverage in a small amount of test generation time, using the fewest registers and functional modules. Comparisons are also made with other behavioral synthesis algorithms which disregard testability in order to establish the efficacy of our approach.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Pages292-297
Number of pages6
ISBN (Print)0897915771, 9780897915779
DOIs
StatePublished - Jan 1 1993
EventProceedings of the 30th ACM/IEEE Design Automation Conference - Dallas, TX, USA
Duration: Jun 14 1993Jun 18 1993

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

Other

OtherProceedings of the 30th ACM/IEEE Design Automation Conference
CityDallas, TX, USA
Period6/14/936/18/93

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Lee, T. C., Jha, N. K., & Wolf, W. H. (1993). Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments. In Proceedings - Design Automation Conference (pp. 292-297). (Proceedings - Design Automation Conference). Publ by IEEE. https://doi.org/10.1145/157485.164897