Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis

Ganesh Lakshminarayana, Anand Raghunathan, Niraj Kumar Jha

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


This paper addresses the problem of synthesizing fault-secure controller/data path circuits from behavioral specifications. We use an iterative improvement based behavioral synthesis framework that performs module selection, clock selection, scheduling, and resource sharing with the aim of minimizing the area of the synthesized circuit, while allowing multicycling, chaining, and module pipelining. We present a dynamic comparison selection algorithm that can be used during behavioral synthesis to determine which intermediate results in the computation need to be secured in order to enable maximal resource sharing. Previous work on synthesizing fault-secure data paths has focussed on ensuring that aliasing cannot occur in any part of the design. We demonstrate that such an approach can lead to unnecessarily large overheads. In order to alleviate the overheads incurred for fault security, our behavioral synthesis framework uses ALiasing Probability analysiS (ALPS) in order to identify resource sharing configurations that reduce area, while introducing a very low probability of aliasing (of the order of 10-10 for a bitwidth of 32) in the resultant data path. We report experimental results for several behavioral descriptions that demonstrate the efficacy of our techniques in synthesizing fault-secure controller/data paths with low overheads.

Original languageEnglish (US)
Pages (from-to)336-345
Number of pages10
JournalProceedings - Annual International Conference on Fault-Tolerant Computing
StatePublished - Jan 1 1996

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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