Abstract
Most of the existing behavioral synthesis systems put emphasis on optimizing area and performance. Only recently has some research been done to consider testability during behavioral synthesis. In our previous work, we integrated hierarchical testability with behavioral synthesis of simple digital data path circuits to synthesize highly testable circuits. In the current work, we consider the testability of complete controller and data path during behavioral synthesis. The methods presented here can easily handle large and complex behavioral descriptions with loops, conditionals, and allow different scheduling constructs, such as pipelining, multicycling, and chaining. The test set for the combined controller/data path is generated during synthesis in a very short time and near 100% fault coverage is obtained for almost all the synthesized circuits at practically zero overheads.
| Original language | English (US) |
|---|---|
| Pages | 91-96 |
| Number of pages | 6 |
| State | Published - 1994 |
| Event | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA Duration: Oct 10 1994 → Oct 12 1994 |
Other
| Other | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors |
|---|---|
| City | Cambridge, MA, USA |
| Period | 10/10/94 → 10/12/94 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering