TY - JOUR
T1 - Automatic test generation for combinational threshold logic networks
AU - Gupta, Pallav
AU - Zhang, Rui
AU - Jha, Niraj K.
N1 - Funding Information:
Manuscript received October 27, 2006; revised September 10, 2007 and October 9, 2007. This work was supported by the National Science Foundation under Grants CCR-0303789 and CCF-0429745. P. Gupta is with the Department of Electrical and Computer Engineering, Vil-lanova University, Villanova, PA 19085 USA (e-mail: pallav.gupta@villanova. edu). R. Zhang is with Mentor Graphics Corporation, San Jose, CA 95131 USA. N. K. Jha is with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA (e-mail: jha@princeton.edu). Digital Object Identifier 10.1109/TVLSI.2008.2000671 Fig. 1. Example for demonstrating linear separability. The hyperplane separates the true and false vertices of a threshold function.
PY - 2008/8
Y1 - 2008/8
N2 - We propose an automatic test pattern generation (ATFG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs), single electron transistor (SET), and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic which has been integrated on top of an existing computer-aided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling, backed by HSPICE simulations, to show that many cuts and shorts in RTD-based threshold gates are equivalent to stuck-at faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuck-at faults in their threshold network implementations.
AB - We propose an automatic test pattern generation (ATFG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs), single electron transistor (SET), and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic which has been integrated on top of an existing computer-aided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling, backed by HSPICE simulations, to show that many cuts and shorts in RTD-based threshold gates are equivalent to stuck-at faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuck-at faults in their threshold network implementations.
KW - Computer-aided design for nanotechnologies
KW - Resonant-tunneling diodes
KW - Test generation
KW - Threshold circuits
UR - http://www.scopus.com/inward/record.url?scp=48349135244&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=48349135244&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2008.2000671
DO - 10.1109/TVLSI.2008.2000671
M3 - Article
AN - SCOPUS:48349135244
SN - 1063-8210
VL - 16
SP - 1035
EP - 1045
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 8
M1 - 4570482
ER -