Automatic test generation for combinational threshold logic networks

Pallav Gupta, Rui Zhang, Niraj Kumar Jha

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

We propose an automatic test pattern generation (ATFG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs), single electron transistor (SET), and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic which has been integrated on top of an existing computer-aided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling, backed by HSPICE simulations, to show that many cuts and shorts in RTD-based threshold gates are equivalent to stuck-at faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuck-at faults in their threshold network implementations.

Original languageEnglish (US)
Article number4570482
Pages (from-to)1035-1045
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume16
Issue number8
DOIs
StatePublished - Aug 1 2008

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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