TY - GEN
T1 - Automatic instruction scheduler retargeting by reverse-engineering
AU - Bridges, Matthew J.
AU - Vachharajani, Neil
AU - Ottoni, Guilherme
AU - August, David I.
PY - 2006
Y1 - 2006
N2 - In order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a compiler to produce such code, it must avoid structural hazards by being aware of the processor's available resources and of how these resources are utilized by each instruction. Unfortunately, the most prevalent approach to constructing such a scheduler, manually discovering and specifying this information, is both tedious and error-prone. This paper presents a new approach which, when given a processor or processor model, automatically determines this information. After establishing that the problem of perfectly determining a processor's structural hazards through probing is not solvable, this paper proposes a heuristic algorithm that discovers most of this information in practice. This can be used either to alleviate the problems associated with manual creation or to verify an existing specification. Scheduling with these automatically derived structural hazards yields almost all of the performance gain achieved using perfect hazard information.
AB - In order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a compiler to produce such code, it must avoid structural hazards by being aware of the processor's available resources and of how these resources are utilized by each instruction. Unfortunately, the most prevalent approach to constructing such a scheduler, manually discovering and specifying this information, is both tedious and error-prone. This paper presents a new approach which, when given a processor or processor model, automatically determines this information. After establishing that the problem of perfectly determining a processor's structural hazards through probing is not solvable, this paper proposes a heuristic algorithm that discovers most of this information in practice. This can be used either to alleviate the problems associated with manual creation or to verify an existing specification. Scheduling with these automatically derived structural hazards yields almost all of the performance gain achieved using perfect hazard information.
KW - Automatic retargeting
KW - Compilers
KW - Instruction scheduling
KW - Reverse-engineering
KW - Structural hazard
UR - http://www.scopus.com/inward/record.url?scp=33746062442&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33746062442&partnerID=8YFLogxK
U2 - 10.1145/1133255.1134008
DO - 10.1145/1133255.1134008
M3 - Conference contribution
AN - SCOPUS:33746062442
SN - 1595933204
SN - 9781595933201
T3 - Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)
SP - 228
EP - 238
BT - PLDI 2006 - Proceedings of the 2006 ACM SIGPLAN Conference on Programming Language Design and Implementation
T2 - PLDI 2006 - 2006 ACM SIGPLAN Conference on Programming Language Design and Implementation
Y2 - 10 June 2006 through 16 June 2006
ER -