Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Hardware platforms comprise general-purpose processors and application-specific accelerators. Unlike processors, application-specific accelerators often do not have clearly specified architecture-level models/specifications (the instruction set architecture or ISA). This poses challenges to the development and verification/validation of firmware/software for these accelerators. Manually writing architecture-level models takes great effort and is error-prone. When Register-Transfer Level (RTL) designs are available, they can be a source from which to automatically derive the architecture-level models. In this work, we propose an approach for automatically generating architecture-level models for processors as well as accelerators from their RTL designs. In previous work we showed how to automatically extract the architectural state variables (ASVs) from RTL designs. (These are the state variables that are persistent across instructions.) In this work we present an algorithm for generating the update functions of the model: how the ASVs and outputs are updated by each instruction. Experiments on several processors and accelerators demonstrate that our approach can cover a wide range of hardware features and generate high-quality architecture-level models within reasonable time.

Original languageEnglish (US)
Title of host publicationProceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
EditorsCristiana Bolchini, Ingrid Verbauwhede, Ioana Vatajelu
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages460-465
Number of pages6
ISBN (Electronic)9783981926361
DOIs
StatePublished - 2022
Event2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 - Virtual, Online, Belgium
Duration: Mar 14 2022Mar 23 2022

Publication series

NameProceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022

Conference

Conference2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
Country/TerritoryBelgium
CityVirtual, Online
Period3/14/223/23/22

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Computer Networks and Communications
  • Hardware and Architecture
  • Software
  • Safety, Risk, Reliability and Quality
  • Control and Optimization

Keywords

  • accelerators
  • architectural abstraction
  • Hardware modelling

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