Augmenting modern superscalar architectures with configurable extended instructions

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, however, are limited by a need for generality and for streamlined implementation. The particular needs of one application are balanced against the needs of the full range of applications considered. For this reason, one can "design" a better instruction set when considering only a single application than when considering a general collection of applications. Configurable hardware gives us the opportunity to explore this option. This paper examines the potential for automatically identifying application-specific extended instructions and implementing them in programmable functional units based on configurable hardware. Adding fine-grained reconfigurable hardware to the datapath of an out-of-order issue superscalar processor allows 4-44% speedups on the MediaBench benchmarks [1]. As a key contribution of our work, we present a selective algorithm for choosing extended instructions to minimize reconfiguration costs within loops. Our selective algorithm constrains instruction choices so that significant speedups are achieved with as few as 4 moderately sized programmable functional units, typically containing less than 150 look-up tables each.

Original languageEnglish (US)
Title of host publicationParallel and Distributed Processing - 15 IPDPS 2000 Workshops, Proceedings
Pages941-950
Number of pages10
StatePublished - Dec 1 2000
Event15 Workshops Held in Conjunction with the IEEE International Parallel and Distributed Processing Symposium, IPDPS 2000 - Cancun, Mexico
Duration: May 1 2000May 5 2000

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume1800 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other15 Workshops Held in Conjunction with the IEEE International Parallel and Distributed Processing Symposium, IPDPS 2000
CountryMexico
CityCancun
Period5/1/005/5/00

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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    Zhou, X., & Martonosi, M. R. (2000). Augmenting modern superscalar architectures with configurable extended instructions. In Parallel and Distributed Processing - 15 IPDPS 2000 Workshops, Proceedings (pp. 941-950). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1800 LNCS).