Area Bloating and the Future of Specialization

Throughout history, technology trends have greatly influenced the development of computer architecture. For the past decade, continuing transistor density scaling combined with stalling voltage scaling created great opportunities for specialization. As a step forward from multi-core processors, hardware accelerators make use of vastly available transistors by dedicating them to specific applications, in exchange for performance and energy efficiency. Unfortunately, the scaling of transistor size is now also slowing down. The complete failure of Moore's Law will raise challenges and demand new approaches with specialization. In this work, we model technology scaling, accelerator scaling, and chip scaling to determine future demands of hardware acceleration in a collection of benchmarks for the next eight technology nodes. We show that if current approaches continue, area is becoming a major limiting factor of achievable performance. In a phenomenon we call area bloating, the area and hence manufacturing cost of chips can increase by at least 78.4 × and 117.4 × respectively from 3nm to A1.8 to match performance gain expectations like those in the past. 3D stacking can deliver more area under the same footprint, at the cost of multiplied power density. But for a limited number of layers, different from the dark silicon prediction, power density plateaus and silicon can be kept bright under liquid cooling. Architectural innovation is required to combat area bloating. We present several directions for future studies. Reduced levels of integration and reduced levels of specialization can help future accelerators adapt to these new trends. By adding limited generality to accelerators, reconfigurable specialization can combat area bloating in platform-specific SoCs, saving significant amounts of area. Future architectures must also consider longevity as chip lifetime increases as a result of slow adoption.