Application and architectural bottlenecks in large scale distributed shared memory machines

A number of researchers have presented architectural techniques for scaling a cache coherent shared address space to much larger processor counts. The present paper examines the extent to which applications can achieve reasonable performance on such large-scale, cache-coherent, distributed shared address space machines, by determining the problems sizes needed to achieve a reasonable level of efficiency. It also looks at how much programming effort and optimization is needed to achieve high efficiency beyond that needed at small processor counts. For each application, the main architectural bottlenecks are discussed that prevent smaller problem sizes or less optimized programs from achieving good efficiency.