Analysis towards minimization of total SRAM energy over active and idle operating modes

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23 Scopus citations


Computational requirements in highly energy constrained applications are driving the need for ultra-low-power processors. In such devices SRAMs pose a primary energy limitation. This paper analyzes SRAM energy in practical applications using state-of-the-art power-management techniques. The design targets and array biasing for energy minimization are developed. Compared with generic logic, these are characterized by the important difference that SRAMs generally need to retain data. This restricts the use of power-gating for leakage elimination, and thus this paper considers the application of low-leakage data-retention biasing during the idle-mode. The resulting energy tradeoffs have important distinctions, and these are analyzed in the presence of practical variation levels.

Original languageEnglish (US)
Article number5545497
Pages (from-to)1695-1703
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number9
StatePublished - Sep 2011

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


  • CMOS memory circuits
  • SRAM
  • data-retention voltage
  • energy minimization
  • power-aware computing


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